1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved process of isolating active regions within a semiconductor substrate. The improved isolation process involves growing a field oxide, removing a nitride layer, growing and subsequently removing a Kooi oxide, and forming a gate oxide all within a single chamber without opening the chamber to an atmospheric ambient.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
Metal oxide semiconductor (MOS) transistors (i.e., devices) are typically formed in isolated active device regions of a frontside surface of a semiconductor substrate. These active device regions are separated by field regions. Electrically insulating layers of silicon dioxide (i.e., oxide) are usually formed over the field regions (i.e., field oxide), and the MOS transistors are electrically coupled by conductive trace elements called interconnects. An interconnect which overlies field oxide between device active areas may inappropriately function as a gate electrode of a parasitic MOS transistor formed between diffused regions of two adjacent MOS devices. Certain measures must be taken to ensure that any possible operating voltage present between the interconnect and the underlying silicon substrate is not sufficient to invert the substrate surface beneath the interconnect. If the substrate beneath field oxide is allowed to invert, a conductive channel will form between the diffused regions of the parasitic MOS transistor. Current flow through parasitic MOS transistors will either cause more power to be dissipated than expected or, in the extreme, cause the circuit to malfunction.
To avoid parasitic conditions, it becomes necessary to raise the turn-on threshold of any parasitic MOS transistors formed in the field regions. One way to raise the turn-on threshold of parasitic MOS transistors is to increase the thickness of the field oxide. Alternatively, or in addition to increasing field oxide thickness, field region doping levels can be increased.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS, involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, typically before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, it involves many process steps that are conventionally performed in separate processing chambers. The semiconductor wafers are first placed in a thermal oxidation furnace where a pad oxide is grown. The wafers are then removed from the thermal oxidation furnace and transported to a chemical vapor deposition (CVD) chamber where a silicon nitride (Si.sub.x N.sub.y) layer is deposited over the pad oxide. A layer of photoresist is then deposited over the nitride layer. Deposition of photoresist may also involve a separate chamber. The photoresist is then patterned to define active regions and field regions. Patterning of the photoresist is accomplished by exposing selected areas of the photoresist to ultraviolet light. The exposed areas polymerize and become resistant to etching. The wafers are then transferred to a dry etch chamber where the non-polymerized areas are removed. The wafers may then be transferred to a wet etch chamber for removal of the pad oxide over the field regions. The wafers may then be transferred to an implantation chamber where a channel-stop implant is performed. Next the wafers may be transferred back to an etching chamber for stripping of the remaining photoresist. Then the wafers are moved to a thermal wet or dry oxidation chamber where the field oxide is grown. After the field oxide is grown, the wafers are transported to an etch chamber to remove the nitride layer.
During growth of the field oxide, a thin layer of silicon nitride may have formed at the pad oxide/silicon interface near the active region borders, as a result of the reaction between the oxidizing agent and the silicon nitride. The formation of nitride at the edge of the field oxide at the oxide/silicon juncture is called the "Kooi effect". The unwanted nitride or "Kooi ribbon" causes localized thinning of any subsequently grown gate oxide. Thus, to remove the Kooi nitride, the wafers may be moved to an oxidation chamber to grow the pad oxide further in the active regions to consume the Kooi ribbon. Then, the wafers may be moved to a wet etch chamber where the grown oxide is removed. Thus, the grown oxide is termed a "sacrificial oxide". The wafers may then be moved to a dry oxidation chamber to grow the gate oxide. A defect-free, high quality gate oxide without contamination is essential for proper device operation. Finally, the semiconductor devices may be created by depositing and patterning a polysilicon gate over the gate oxide and then doping the source and drain regions.
The LOCOS process described above is a complex process involving many different processing steps. Wafers frequently must be transported between processing chambers. This frequent moving of the wafers inflicts several problems into the process. Repeated moving of the wafers may impose a risk of damaging the wafers. Also, repeated thermal cycling when wafers are moved from warm or thermal processes may result in stress damage to device structures. Furthermore, each time the wafers are removed from a processing chamber, they may be exposed to contaminants that may result in lowering yield. Finally, transportation of wafers between chambers is time consuming and lowers process throughput and efficiency. These effects increase the overall cost of fabrication.
A need therefore exists in producing a process which can advantageously perform LOCOS isolation with a reduction in the aforedescribed detrimental effects of the conventional LOCOS process. Thus, it is desirable to have a process that may impose less risk of damaging the wafers. It is further desirable to have a process that may lessen thermal stress when wafers are removed from processing chambers. Also, it is desirable to lessen the exposure to contaminants outside processing chambers. Moreover, it is desirable to increase the throughput and efficiency of the LOCOS process, thereby lowering overall production cost.